CSIX-PI40-O4-N1【PDF 17/23 页】INTERFACE IP CSIX TO PI40 ORCA 4

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Sheet目录1204

13页 14页 15页 16页 [17页]18页 19页 20页 21页

Lattice Semiconductor

Figure 11. CSIX Outbound Frame Transfer

c6_clk_out_N_ext

c6_parity_out_N_ext

c6_sof_out_N_ext

CSIX-to-PI40 IP Core User’s Guide

c6_data_out_N_ext[31:0]

1,2,3

5,6,7

65,66,

67,68

69,70,

71,72

The AC timing speci?cations for the outbound CSIX port are as follows:

Figure 12. CSIX Outbound AC Timing Speci?cations

tclk_period

c6_clk_out_N_ext

tclk_signal_valid

c6_signal_out_N_ext

Name

tclk_freq

tclk_period

tclk_signal_valid

Description

Clock frequency

Clock period

Signal valid from rising edge of clock

Min.

—

10ns

0.5ns

Max.

100MHz

—

2.4ns

The DC electrical speci?cations for the inbound CSIX port are as follows:

Name

V DDIO

V OH

V OL

I OH

I OL

Description

I/O supply voltage

V OUT high voltage

V OUT low voltage

I OUT at V OH

I OUT at V OL

Min.

2.3V

V DDIO - 0.2V

—

12mA

6mA

Typ.

2.5V

—

—

—

—

Max.

2.7V

—

0.2V

—

—

SERDES Ports

The timing and electrical speci?cations for this interface are covered in the ORCA ORSO82G5 data sheet.

Microprocessor Interface

The timing and electrical speci?cations for this interface are covered in the ORCA Series 4 FPGA data sheet.

17

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